In recent years, a technique has been presented in which a pixel portion of a CMOS image sensor (CIS) and an analog-digital converter (ADC) portion are manufactured as separate chips, the chips are stacked, and the stacked chips are connected to each other. For example, a pixel region of a. CIS is divided into small blocks of 16×16 dots. A chip including a plurality of ADC cells are manufactured as a chip separately from the CIS so that ADCs (ADC cells) corresponding to the respective blocks are arranged in a two-dimensional manner. The ADCs are connected to the respective blocks of the CIS by minute metal junctions. This technique enables an increase in the frame rate, because the technique reduces the number of pixels to be controlled by an ADC in comparison with the conventional column parallel system. In addition, the technique enables a reduction in the chip area of the entire device including the CIS, because the ADCs placed on the sides of the pixels in the conventional column parallel system are superimposed on the pixel region.
An example in which the CIS and the peripheral logic circuit are formed as one unitary piece has been reported. In the example, the pixel portion of the CIS and the peripheral logic circuit including the ADCs are formed as separate chips mutually separated from each other, the chips are bonded to each other in a vertical direction, and the chips are vertically and electrically connected to each other with TSVs. This technique improves the processing performance, because the technique enables the use of optimized processes and circuit configurations for the pixel portion and the logic portion.
It is very difficult to electrically connect chips in which the pixel portion of a CIS and a peripheral logic circuit are separately manufactured. Although microbumps are required to electrically connect an ADC chip with a CIS chip, the pitch of the microbumps is 5 μm or more. For this reason, miniaturization of the connection pitch is difficult, and limits exist for dealing with future increases in the number of pixels in a small-sized CIS. It also has the problem of high costs (thinning, dicing, alignment, and bonding) for bonding chips manufactured separately. The case of bonding a peripheral logic circuit chip to a CIS chip with TSVs also has a similar problem because the pitch of TSVs is 10 μm or more.